An Approach toward Accurately Timed TLM+ for Embedded System Models

Abstract:
To enable the design and verification of complex systems on chip, newmodelling styles for virtual prototypes (VPs) with high communication abstraction were suggested such as the TLM2.0 generic payload transaction or TLM+ transfers. With such abstraction, each driver function of the embedded SW is modelled by a single transaction to transfer a block of data or a data structure. This work presents a methodology to model the timing behaviour for such highly abstracted communication. First, a non-intrusive tracing mechanism for extracting the necessary timing parameters from a simulation of the driver functions is presented. Using this trace file, an offline profiler retrieves the statistics of HW activities and the timing characteristics of the driver functions. Such information is stored in a library. For a simulation with block mode, the timing information in the library is used to time the highly abstracted transactions. In order to deal with multiple accesses to shared resources, a novel scheduling algorithm is developed to determine the additional delays due to conflicting accesses on shared HW modules. Experimental results show an accumulated error of less than 1% and a performance gain of 472.