A Delay Estimation of Rescheduling Schemes for Static Scheduled Processor Architectures

Abstract:
We compare three different rescheduling schemes for statically scheduled processor architectures. One of the rescheduling schemes is software-based while the others are based on hardware support. The rescheduling becomes necessary if the compiler generated schedule for a static scheduled processor architecture must be changed in-the-field because of a permanent fault in the data path of the processor. By comparing the hardware and software-based rescheduling schemes we can show that our proposed software-based rescheduling scheme in many cases reduces the worst-case latency of the executed program in the presence of a permanent fault.