Wafer Based Mask Characterization for Double Patterning Lithography

Abstract:
Double Patterning Technology (DPT) is considered the most acceptable solution for 32nm node lithography. Apart from the obvious drawbacks of additional exposure and processing steps and therefore reduced throughput, DPT possesses a number of additional technical challenges. This relates to exposure tool capability, the actual applied process in the wafer fab but also to mask performance. This paper will focus on the latter. We will report on the performance of a two-reticle set based on a design developed to study the impact of mask global and local placement errors on a DPT dual line process. For 32 nm node lithography using DPT a reticle to reticle overlay contribution target of <=1.5nm has been proposed. Reticle based measurements have shown that this proposed target can be met for standard overlay features and dedicated DPT features. In this paper we will present experimental intra field overlay wafer data resulting from the earlier mentioned reticle set. The reticles contain a 13x19 array of modules comprising various standard overlay features such as ASML overlay gratings and bar-in-bar overlay targets. Furthermore the modules contain split 40nm half pitch DPT features. The reticles have been exposed on an ASML XT:1700i on several wafers in multiple fields. Reticle to reticle overlay contribution has been studied in resist (double exposure) and using the IMEC dual line process [1] (DPT). We will show that the reticle to reticle overlay contribution on the wafer is smaller than 1.5nm (1x). We will compare the wafer data with the reticle data, study the correlation and show that reticle to reticle overlay contribution based single mask registration measurements can be used to qualify the reticle to reticle overlay contribution on wafer.