A Compact Multi-Tone Test Generator for RF ICs Using a Σ Δ-PLL

Abstract:
A new approach to adding built-in self test (BIST) capabilities to integrated RF transceiver chips is presented. An area efficient, all-digital building block generates multitone FM test signals in conjunction with a fractional-N phase locked loop without compromising the performance of the RF transceiver. The block itself is fully testable and consumes a chip area of only 0.015mm² in a 130nm CMOS technology. The spectral quality and reproducibility of the test signals are suitable for intermodulation distortion tests or PLL loop and jitter transfer measurements.