Impact of the Level of Negative Gate Voltage on the Temperature Measurement during Power Cycling Testing of SiC MOSFETs
Conference: CIPS 2024 - 13th International Conference on Integrated Power Electronics Systems
03/12/2024 - 03/14/2024 at Düsseldorf, Germany
Proceedings: ETG-Fb. 173: CIPS 2024
Pages: 7Language: englishTyp: PDF
Authors:
Heimler, Patrick; Reiter, Kristiane; Guenther, Marco; Lutz, Josef; Basler, Thomas (Chemnitz University of Technology, Chair of Power Electronics, Chemnitz, Germany)
Abstract:
In this work, test specimens from two different manufacturers with an RDS(ON) of 80 mOmega with a blocking capability of 1.2 kV in TO-247 housing were selected to investigate the influence of the level of negative gate voltage for accurate temperature measurement during power cycling. All devices failed with an increase in forward voltage, confirmed by the failure analysis. No influence of different magnitudes of negative gate voltage on the power cycling stability was found. However, a shift of the threshold voltage by up to 1.5 V is possible depending on the test conditions, which has a strong influence on the temperature measurement when the n-channel is not completely closed.