A Systematical and Analytical Driver Layout Design Procedure for Parallel GaN GIT Power Semiconductors

Abstract:
The increase in switching frequencies brings multiple benefits in size and cost reductions. However, it also introduces new challenges related to printed circuit board (PCB) design. The paper explores and presents an in-depth and systematic method to analytically analyze, design, and layout the gate driver circuit on a PCB. The developed, generally usable highfrequency analysis methodology is tailored for Gallium Nitride (GaN) gate injection transistor (GIT) power modules to be used in medium power (>100 kVA) applications, such as inverters. The methodology includes analytical methods to estimate the trace inductances, planning for symmetrical component arrangements, and studies on the direction of the flow of current in the traces in different switching states to prioritize targets for reducing parasitic inductance, layer partitioning, and component placements. The single analysis elements of the methodology are suitable for common use, e.g., with other driver ICs or semiconductor types. To further substantiate the methodology, a case study using an Infineon 1EDF5673K GaN GIT driver is presented. The PCB design is presented, and the proposed methodology is validated through a test setup. The results show that the proposed methodology can effectively achieve symmetrical driving.