Optimized Super Cascode Circuit for Electrical Testing under High Frequencies, Voltages and Voltage Gradients

Abstract:
Current test systems for power electronic components are unable to handle the combination of high frequencies, high voltage amplitudes and high voltage gradients economically as well as technically. An innovative solution is the super cascode circuit, which is extensively described in several publications. This configuration consists of various cascaded semiconductor switches. In this publication the JFETs are based on SiC technology to provide a high blocking voltage. This enables the super cascode to be optimized for high-voltage scenarios. In the context of the running project the parameters of a single super cascode circuit were improved. Additionally the cascode was optimized for the use in a half-bridge setup.