Real Time Floating Point SAR Focusing on FPGA
Conference: EUSAR 2024 - 15th European Conference on Synthetic Aperture Radar
04/23/2024 - 04/26/2024 at Munich, Germany
Proceedings: EUSAR 2024
Pages: 6Language: englishTyp: PDF
Authors:
Mandapati, Srikanth; Balss, Ulrich; Breit, Helko
Abstract:
Due to the demand for faster processing times, less required space, and efficienct power consumption in the era of high-performance computing (HPC) as well as onboard processing, the use of Graphics Processing Units (GPUs) and in particular Field-Programmable Gate Arrays (FPGAs) have emerged as powerful and versatile solutions for accelerating data workloads. Offloading compute-intensive workloads from the Central Processing Unit (CPU) to these accelerating cards enables faster processing, analysis of large data, and resulting in improved time-to-insight and decision-making capabilities. Specifically, FPGAs can deliver exceptional performance, energy efficiency and flexibility in contrast to GPUs. By taking these advantages of the FPGAs on the data accelerator cards, the Synthetic Aperture Radar (SAR) image focusing algorithm is implemented on an AMD Xilinx Alveo U55C card. The processor is developed in floatingpoint on the FPGA to achieve higher accuracy and can focus an area covering 375km2 in approximately 1:5 s.