Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells

Abstract:
There are currently multiple investigations of various RISC-V architectures for different applications from single-core based edge processors to powerful multi-core systems for High-Performance Computing (HPC). We have recently introduced a many-core GPC (Grid of Processing Cell) architecture based on configurable modified RISC-V RocketTiles with local memories and systembus communication, which was demonstrated and evaluated using RTL simulation by simple distributed software programs. In this work, we have refined and extended our development by two communication schemes for direct intercell processor communication between neighboring cells: via (i) shared memory and via (ii) RISC-V Control and Status Registers (CSRs). Both alternatives are implemented on an AMD VCU108 FPGA and as chip layouts based on SkyWater 130 nm CMOS technology. The performance is evaluated by a distributed systolic matrix multiplication algorithm with different grid sizes.