A Rate-Parametric Dataflow Language for a Manual Controllable CGRA Compilation Flow

Abstract:
Coarse Grained Reconfigurable Arrays (CGRAs) are particularly interesting accelerators because they uniquely combine domain-specific configurability with high energy-efficiency. To facilitate a manual controllable compilation flow for CGRAs, we have presented a flexible Dataflow Graph (DFG) language in previous work. This language serves as human understandable modeling language and intermediate representation in the compilation flow. However, up to now this language assumes fixed and idealized hardware block functionalities. This assumption is problematic when targeting contemporary CGRA accelerators. Therefore, we present an extension to this language which supports important configuration parameters of these hardware blocks. We achieve this by introducing parametric template operations into our DFG language. We show the semantic soundness of our language extension by providing a reduction to a well-known dataflow model of computation. A preliminary evaluation in this paper shows the applicability of the extended language for targeting complex hardware block functionalities of a contemporary and commercially available CGRA.