Modeling for Synthesis of Deadlock-Free and Fault-Tolerant Networks-on-Chip

Abstract:
The emergence of Networks-on-Chip (NoC) as a promising solution for on-chip communication in highly integrated System-on-Chips (SoCs) introduces significant design challenges. This report provides an overview of the modeling for synthesis of deadlock-free and fault-tolerant NoC using Integer Linear Programming (ILP). The adaptability of the proposed ILP method is a noteworthy feature. Through evaluations, we demonstrate its capability to consistently obtain optimal solutions. Alternatively, within a shorter time frame, it yields competitive results comparable to heuristic methods. Additionally, a comprehensive case study on the deadlock-free and fault-tolerant routing construction and application mapping is presented. This study illustrates the construction of routing paths for both normal operation and fault cases across diverse topologies. The proposed approach optimizes routing paths during normal operation while also aiming to make alternative routing paths optimal. Therefore it effectively minimizes performance degradation in fault cases.