Analyzing Local RISC-V Interrupt Latencies with Virtual Prototyping

Abstract:
The gem5 simulator is a state-of-the-art tool for modeling RISC-V processors. It offers simulation at the microarchitectural level. Thereby, it enables not only functional testing but evaluation of extra-functional system properties like timing or energy efficiency. Since embedded systems often interact with their peripherals using interrupts, these properties play a crucial role in evaluating overall platform performance. Currently, gem5 only supports parts of the interrupt functionality for external devices specified for the RISC-VISA, namely external interrupt. Local interrupts, on the other hand, lack simulator support. However, especially in the mobile context, their functionality can be crucial, since often only a few interrupt sources are used. These interrupts need fast and efficient handling. The paper at hand extends the RISC-V implementation of gem5 by local interrupts as defined in the RISC-V specification for direct interrupt management. This extension is then used to perform a comprehensive analysis of the timing behavior of local and external interrupts.