Verification of Function Stable Muller C-element in FPGA

Abstract:
The goal of the paper is to design a function stable Muller C-element in Field Programmable Gate Array (FPGA). It is a prerequisite for correct asynchronous designs in FPGA. The trick is to provide an easy-to-understand measurement and test to guarantee the correct behavior of the circuitry. The feedback path of the circuitry must have a smaller delay than the forward path of the circuitry. The paper deals with path delays in FPGA at low level, their determination by oscillation and a test for verification. The knowledge gained is intended to serve the asynchronous design process.