Self-turn-on-free criteria for MOS gate power device and circuit

Abstract:
The improved power density of the emerging power electronics systems demands a significant enhancement in the switching speed to reduce the magnetic components and heat-sink volume. The self-turn-on phenomenon has emerged as a major issue in the design of power circuits and power device packaging to prevent the power loss increase and device failure. The voltage drop across the gate resistance owing to the displacement current with a high dV/dt of the collector voltage has been identified as the major cause of the self-turn-on mechanism. In this study, we focused on the dI/dt of the collector current during switching because stray inductance management is a critical issue in preventing the self-turn-on in future. We analyze the self-turn-on phenomenon from a different perspective via TCAD simulation, and propose countermeasures for stray inductance management in gate and emitter wirings as well as device structure design guidelines.