Investigation of long-term drift effects of SiC MOSFETs under power cycling like gate conditions

Abstract:
Power cycling tests are an established routine in the qualification process of power electronic devices. New challenges however evolve from the application to wide band gap devices: In case of SiC MOSFETs, the threshold voltage Vth is continuously shifting during the test execution affecting the on-state resistance RDS;on and thus the induced thermomechanical stress as well as a reliable failure indication. The impact of such drift effects – solely caused by the gate bias – is investigated in this work by applying similar gate conditions as during a power cycling test, but at constant temperature without load current flow. This way, any influence of package degradations can be excluded. A test setup was developed for this investigation, allowing the in-line monitoring of DeltaVth and DeltaRDS;on. The impact of the voltage class, the gate turn-off voltage and the temperature are investigated and discussed. A modelling approach and a compensation concept are proposed in addition, revealing that the proportion of the channel resistance on RDS;on is the decisive parameter when evaluating the impact of DeltaVth on DeltaRDS;on and that an additional drift effect – not covered by DeltaVth – can occur under bipolar switching conditions.