Dealing with Clock Domain Crossing in Multiphase Clock Time-to-Digital Converters using Multiplexer Synchronizers

Abstract:
In this paper, timing violations, such as metastability of flip-flops caused by crossing clock domains, are vividly examined and discussed. It is explained why a parallel signal must not be transferred to another clock domain with single two-flip-flop synchronization circuits. The multiplexer synchronization topology is presented as a solution. It is based on the simple two-flip-flop synchronization and extended to use parallel data, which means that the mathematical theory of the mean time between failures for the two-flip-flop synchronization circuit is still valid. At the end, the theoretical concept is transferred and explained for use in the practical application of the multiphase clock time-to-digital converter.