Pin-Type Based VLSI Partitioning

Abstract:
For deeply modeling and verification of feedback asynchronous and synchronous circuitry it is essential to partition the circuitry into sub-structures. For this, many graph-theoretical approaches for VLSI partitioning are investigated. In this paper, we present a novel partitioning approach based on pin-types. We state the underlying data structure to classify a pin as input, output, state, feed, cycle and iter, respectively. The employed data structure provides the matrix representation in different normal forms. We show the unique partitioning of a given circuit structure considered as a directed graph (network) into its regular and singular parts. Additionally, we upgrade the low level partitioning technique to a high level abstraction and state our formalism for functionally stable and unique parallel composition and decomposition of network under balance (NUB).