TSV CMP Process Development and Pitting Defect Reduction

Abstract:
Three-dimensional (3D) chip integration is one of the most important and main trends in the advance packaging technology. This technology calls for the stacking of integrated circuits interconnected by through silicon via (TSV). TSV technology not only exponentially increases connection efficiency between dies, but also it can be practically integrated into current IC manufacture processes with minimal impact on both FEOL and BEOL design and processing. A TSV chemical mechanical polishing (CMP) process with two polishing steps, including Cu polishing, and Cu barrier/isolation layers polishing, has been proposed to form via-middle TSV structures. Although TSV CMP is generally compatible with traditional IC CMP facilities and guidelines, emerging challenges that arise from specific designs in TSV architectures, such as bulky overburdens and multilayer interfaces, still need to overcome. The TSV special structure require the CMP process with higher Cu removal rate, higher barrier/oxide removal rate, higher oxide/Si3N4 selectivity, low dishing and good topography performance. In this paper, we focus on Cu TSV CMP process development with good performance by slurry screening, formulation and process fine tuning. The integrated process optimizations of Cu CMP process and electrochemical planting (ECP) of Cu have been evaluated to reduce TSV pitting defect post CMP. Finally one robust Cu TSV CMP process with good performance is proposed. Key word: TSV, slurry, selectivity, pitting, profile