A radiation hard δ Σ ADC in 130 nm CMOS
Conference: PRIME 2012 - 8th Conference on Ph.D. Research in Microelectronics & Electronics
06/12/2012 - 06/15/2012 at Aachen, Germany
Proceedings: PRIME 2012
Pages: 4Language: englishTyp: PDF
Personal VDE Members are entitled to a 10% discount on this title
Authors:
Verbeeck, Jens; Steyaert, Michiel (KU Leuven, Dept. ESAT-MICAS, Kasteelpark Arenberg 10, 3001 Heverlee, Belgium)
Van Uffelen, Marco (Fusion for Energy, c/Josep,n° 2, Torres Diagonal Litoral, Ed. B3, 08019 Barcelona, Spain)
Leroux, Paul (KU Leuven, Dept. ESAT-MICAS, Kasteelpark Arenberg 10, 3001 Heverlee, Belgium )
Abstract:
In this paper a radiation tolerant δ Σ ADC is presented. The design features a 1.5 V, 17 bit Δ Σ ADC consuming 4.35 mW at a sample frequency of 1 MHz. The ADC features a bandwidth of 1 kHz and utilizes a correlated double sampling technique (CDS) to remove offset and 1/f noise. The circuit maintains its 17 bit resolution upon a simulated radiation dose exceeding 1 MGy and varying temperatures between 0 ºC and 85 ºC. Keywords- Analog integrated circuits, Switched capacitor circuits, CMOS technology, Reactor instrumentation