Digital mismatch calibration of charge redistribution SAR ADCs

Abstract:
A low power, small area 12 bit 100 kS/s successive approximation charge redistribution ADC in 150 nm CMOS technology is presented using 43 fF metal-insulator-metal capacitors. Capacitor mismatch which limits the circuit performance and yield is analysed. A mismatch estimation and correction scheme is explained in detail which is able to compensate for mismatch variation of more than ±3 times of the standard deviation. The estimation algorithm is optimized to use only a zero voltage input signal for parameter extraction. In order to achieve INL performance better than ±1 LSB an additional bit of resolution is employed for calibration without additional analog circuitry.