Sequential Hierarchical Model-order Reduction for Robust Design of Parameter-varying Systems

Inhalt:
In this paper we introduce a method for the hierarchical model order reduction of parameter-varying analog circuits. A new concept is presented that reduces the circuit’s blocks to build a reduced overall model that does not violate a predefined error bound. An additional acceleration of the reduction process is achieved by introducing a sequential workflow of the reduction algorithm. Finally for illustration, we apply the overall procedure to the operational amplifier OpAmp 741 and compare it to the standard methods.